There has been great progress in the field of integrated circuit fabrication. The trend has been to reduce the size of semiconductor devices. In addition, multiple layers of interconnections between devices are now used. A subsequent layer is generally formed on an underlying layer. In order to achieve a better topography, a planarization process is quite often used to obtain a planar surface. Thus, planarization is the key way to make sure that a layer has a planar surface. If one of the multiple layers has poor topography, then this results in alignment problems for subsequent layers.
Typically, during the formation of ICs, borophosphosilicate glass (BPSG) is used as an interlayer dielectric for integrated circuits. This is due to the fact that BPSG is applied in liquid form and therefore exhibits good planarization capabilities. The BPSG is formed by using a low pressure chemical vapor deposition (LPCVD) process using a reactant gas, such as tetraethylorthosilicate (TEOS) to which are added dopant gases, for example phosphine (PH.sub.3) and diborane (B.sub.2 H.sub.6).
Referring to FIG. 1, when a BPSG layer 101 is used as an interlayer dielectric, it is often formed over and between underlying structures 103, such as gate structures and similar devices. In a typical process, the BPSG layer is first reflowed and then planarized using a chemical planarization process (CMP). Typically, the underlying structures have a top cap layer of silicon nitride that is used as a stop layer for the CMP process.
Planarization by the CMP presents several problems. The removal rate of the BPSG oxide by the CMP is higher than the removal rate of the cap nitride on the underlying structures 103, causing a dishing effect 105 in wide trenches. This dishing effect degrades the planarity of a layer, and it also impacts the yield of the device. Further, the CMP process produces "chatter mark defects" 109 in the BPSG layer 101 and on the underlying structures 103.
As semiconductor devices are scaled down, it is more important than ever to have a planar defect free BPSG surface. The present invention provides a method to achieve an improved planar and defect free surface for the BPSG layer.